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FEATURES
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LTC2451 Ultra-Tiny, 16-Bit DS ADC with I2C Interface DESCRIPTION
The LTC(R)2451 is an ultra-tiny, 16-bit, analog-to-digital converter. The LTC2451 uses a single 2.7V to 5.5V supply, accepts a single-ended analog input voltage and communicates through an I2C interface. The converter is available in an 8-pin, 3mm x 2mm DFN or TSOT-23 package. It includes an integrated oscillator that does not require any external components. It uses a delta-sigma modulator as a converter core and provides single-cycle settling time for multiplexed applications. The LTC2451 includes a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude lower than conventional converters. The LTC2451 is capable of up to 60 conversions per second and, due to the very large oversampling ratio, has extremely relaxed antialiasing requirements. In the 30Hz mode, the LTC2451 includes continuous internal offset calibration algorithms which are transparent to the user, ensuring accuracy over time and over the operating temperature range. The converter has external REF+ and REF - pins and the input voltage can range from VREF- to VREF+. If VREF+ = VCC and VREF- = GND, the input voltage can range from GND to VCC. Following a single conversion, the LTC2451 can automatically enter sleep mode and reduce its power to less than 0.2A. If the user reads the ADC once per second, the LTC2451 consumes an average of less than 50W from a 2.7V supply.
Integral Nonlinearity, VCC = 3V
3 2 2.7V TO 5.5V 0.1F REF + 10F INL (LSB) 1 0 -1 TA = - 45C, 25C -2
2451 TA01a
GND to VCC Single-Ended Input Range 0.02LSB RMS Noise 2LSB INL, No Missing Codes 1LSB Offset Error 4LSB Full-Scale Error Programmable 30/60 Conversions per Second Single Conversion Settling Time for Multiplexed Applications Single-Cycle Operation with Auto Shutdown 400A Supply Current 0.2A Sleep Current Internal Oscillator--No External Components Required Single Supply, 2.7V to 5.5V Operation 2-Wire I2C Interface Ultra-Tiny 3mm x 2mm DFN or TSOT-23 Package
APPLICATIONS
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System Monitoring Environmental Monitoring Direct Temperature Measurements Instrumentation Industrial Process Control Data Acquisition Embedded ADC Upgrades
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. No Latency and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.
TYPICAL APPLICATION
1k IN SENSOR 0.1F REF -
VCC
SCL SDA 2-WIRE I2C INTERFACE
LTC2451 GND
TA = 90C
-3
0
0.5
1 1.5 2 INPUT VOLTAGE (V)
2.5
3
2451 TA01b
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LTC2451 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) ................................... -0.3V to 6V Analog Input Voltage (VIN) ............ -0.3V to (VCC + 0.3V) Reference Voltage (VREF+, VREF -) ...-0.3V to (VCC + 0.3V) Digital Voltage (VSDA, VSCL) .......... -0.3V to (VCC + 0.3V)
Storage Temperature Range................... -65C to 150C Operating Temperature Range LTC2451C ................................................ 0C to 70C LTC2451I.............................................. -40C to 85C
PIN CONFIGURATION
TOP VIEW TOP VIEW GND REF- REF+ VCC 1 2 3 4 9 8 7 6 5 SDA SCL IN GND GND 1 REF- 2 REF+ 3 VCC 4 8 SDA 7 SCL 6 IN 5 GND
DDB PACKAGE 8-LEAD (3mm 2mm) PLASTIC DFN C/I GRADE TJMAX = 125C, JA = 76C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 C/I GRADE TJMAX = 125C, JA = 140C/W
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C LTC2451CDDB#TRMPBF LTC2451CDDB#TRPBF LDGQ 8-Lead Plastic (3mm x 2mm) DFN LTC2451IDDB#TRMPBF LTC2451IDDB#TRPBF LDGQ 8-Lead Plastic (3mm x 2mm) DFN LTC2451CDDB#TRMPBF LTC2451CTS8#TRPBF LTDNS 8-Lead Plastic TSOT-23 LTC2451IDDB#TRMPBF LTC2451ITS8#TRPBF LTDNS 8-Lead Plastic TSOT-23 TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Offset Error Drift Gain Error Gain Error Drift Transition Noise Power Supply Rejection DC Power Supply Rejection DC
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
CONDITIONS (Note 3) (Note 4) 30Hz Mode 60Hz Mode
l l l l l
MIN 16
TYP 2 0.08 0.5 0.02 0.01 0.02 1.4 80 80
MAX 10 0.5 2 0.02
UNITS Bits LSB mV mV LSB/C % of FS LSB/C VRMS dB dB
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30Hz Mode 60Hz Mode
2
LTC2451 ANALOG INPUT AND REFERENCES
SYMBOL VIN VREF+ VREF- CIN IDC_LEAK(VIN) PARAMETER Input Voltage Range Positive Reference Voltage Range Negative Reference Voltage Range IN Sampling Capacitance IN DC Leakage Current
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
CONDITIONS VREF+ - VREF- 2.5V VREF+ - VREF- 2.5V VIN = GND (Note 8) VIN = VCC (Note 8) VREF = 5V (Note 8) MIN l VREF- l VCC - 2.5 l 0
l l l
TYP
MAX VREF+ VCC VCC - 2.5 10 10 10
IDC_LEAK(REF+, REF-) REF+, REF- DC Leakage Current Input Sampling Current (Note 5) ICONV
-10 -10 -10
0.35 1 1 1 50
UNITS V V V pF nA nA nA nA
POWER REQUIREMENTS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Sleep
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
CONDITIONS
l l l
MIN 2.7
TYP
MAX 5.5 700 0.5
UNITS V A A
400 0.2
I2C INPUTS AND OUTPUTS
SYMBOL VIH VIL VHYS VOL IIN CI CB
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V. (Note 2)
PARAMETER High Level Input Voltage Low Level Input Voltage Hysteresis of Schmidt Trigger Inputs Low Level Output Voltage (SDA) Input Leakage Capacitance for Each I/O Pin Capacitance Load for Each Bus Line CONDITIONS
l l
MIN 0.7VCC 0.05VCC -1 10
TYP
MAX 0.3VCC 0.4 1 400
(Note 3) I = 3mA 0.1VCC VIN 0.9VCC
l l l l l
UNITS V V V V A pF pF
I2C TIMING CHARACTERISTICS
SYMBOL tCONV tCONV fSCL tHD(SDA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) tBUF
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V. (Notes 2, 7)
PARAMETER Conversion Time Conversion Time SCL Clock Frequency Hold Time (Repeated) Start Condition Low Period of the SCL Pin High Period of the SCL Pin Set-Up Time for a Repeated Start Condition Data Hold Time Data Set-Up Time Rise Time for SDA/SCL Signals Fall Time for SDA/SCL Signals Set-Up Time for Stop Condition Bus Free Time Between a Stop and Start Condition CONDITIONS 30Hz Mode 60Hz Mode
l l l l l l l l l
(Note 6) (Note 6)
l l l l
MIN 26 13 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3
TYP 33.2 16.6
MAX 46 23 400
0.9 300 300
UNITS ms ms kHz s s s s s ns ns ns s s
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LTC2451 I2C TIMING CHARACTERISTICS
SYMBOL tOF tSP PARAMETER Output Fall Time VIH(MIN) to VIL(MAX) Input Spike Suppression
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 2, 7)
CONDITIONS Bus Load CB 10pF to 400pF (Note 6)
l l
MIN 20 + 0.1CB
TYP
MAX 250 50
UNITS ns ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V, unless otherwise specified. Specifications apply to both 30Hz and 60Hz modes unless otherwise specified. VREF = VREF+ - VREF-, VREFCM = (VREF+ + VREF-)/2, FS = VREF+ - VREF-; VREF- VIN VREF+ Note 3. Guaranteed by design, not subject to test.
Note 4. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Guaranteed by design, test correlation and 3-point transfer curve measurement. Note 5. Input sampling current is the average input current drawn from the input sampling network while the LTC2451 is actively sampling the input. CB = capacitance of one bus line in pF. Note 6. CB = capacitance of one bus line in pF. Note 7. All values refer to VIH(MIN) and VIL(MAX) levels. Note 8. A positive current is flowing into the DUT pin.
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C; graphs apply to both 30Hz and 60Hz modes, unless otherwise noted. Integral Nonlinearity VCC = VREF+ = 5V
3 2 1 INL (LSB) INL (LSB) 0 -1 -2 -3 TA = - 45C, 25C, 90C 3 2 1 0 TA = - 45C, 25C, 90C -1 -2 -3 INL (LSB)
Integral Nonlinearity VCC = 5V, VREF+ = 3V
3 2 1 0 -1
Integral Nonlinearity VCC = VREF+ = 3V
TA = 90C
TA = - 45C, 25C -2 -3
0
1
2 3 INPUT VOLTAGE (V)
4
5
2451 G01
0
0.5
1 1.5 2 INPUT VOLTAGE (V)
2.5
3
2451 G02
0
0.5
1 1.5 2 INPUT VOLTAGE (V)
2.5
3
2451 G03
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LTC2451 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C; graphs apply to both 30Hz and 60Hz modes, unless otherwise noted. Maximum INL vs Temperature
5.0 4.5 4.0 3.5 OFFSET (mV) INL (LSB) 3.0 2.5 2.0 1.5 1.0 0.5 0 -50 -25 25 50 0 TEMPERATURE (C) 75 100
2451 G04
Offset Error vs Temperature 30Hz Mode
0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 VCC = 3V VCC = 4.1V VCC = 5V OFFSET (mV) 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 25 50 0 TEMPERATURE (C) 75 100
2451 G05
Offset Error vs Temperature 60Hz Mode
VCC = 4.1V VCC = 5V VCC = 3V
VCC = 5V, 4.1V, 3V
0.00 -50
-25
0.00 -50
-25
25 50 0 TEMPERATURE (C)
75
100
2451 G06
Gain Error vs Temperature
10 9 8 GAIN ERROR (LSB) 7 6 5 4 3 2 1 0 -50 -25 25 50 0 TEMPERATURE (C) 75 100
2451 G07
Transition Noise vs Temperature
3.0 2.5 2.0 1.5 1.0 0.5 0 -50 VCC = 5V VCC = 3V 3.0 2.5 2.0 1.5 1.0 0.5 0 -25 0 25 50 TEMPERATURE (C) 75 100
2451 G08
Transition Noise vs Output Code
VCC = 3V VCC = 4.1V VCC = 5V
TRANSITION NOISE RMS (V)
TRANSITION NOISE RMS (V)
VCC = 5V
VCC = 3V
0
16384
32768 49152 OUTPUT CODE
65536
2451 G09
Conversion Mode Power Supply Current vs Temperature
600 500 400 300 200 100 0 -50 VCC = 5V VCC = 4.1V SLEEP CURRENT (nA) 250
Sleep Mode Power Supply Current vs Temperature
10000 AVERAGE POWER DISSIPATION (W)
Average Power Dissipation vs Temperature VCC = 3V, 30Hz Mode
CONVERSION CURRENT (A)
200
VCC = 5V
1000
25Hz OUTPUT SAMPLE RATE 10Hz OUTPUT SAMPLE RATE
150 VCC = 4.1V 100
VCC = 3V
100 1Hz OUTPUT SAMPLE RATE 10
50
VCC = 3V
-25
0 25 50 TEMPERATURE (C)
75
100
2451 G10
0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
2451 G11
1 -50
-25
0 25 50 TEMPERATURE (C)
75
100
2451 G12
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LTC2451
modes, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Average Power Dissipation vs Temperature VCC = 3V, 60Hz Mode
10000 AVERAGE POWER DISSIPATION (W) 0 -20 REJECTIOIN (dB) 25Hz OUTPUT SAMPLE RATE 10Hz OUTPUT SAMPLE RATE 100 1Hz OUTPUT SAMPLE RATE 10 -100 1 -50 -120 1 -40 -60 -80
TA = 25C; graphs apply to both 30Hz and 60Hz
Power Supply Rejection vs Frequency at VCC
1000
30Hz MODE, 60Hz MODE
-25
0 25 50 TEMPERATURE (C)
75
100
2451 G13
10
100 1k 10k 100k FREQUENCY AT VCC (Hz)
1M
10M
2451 G14
Conversion Period vs Temperature 30Hz Mode
44 42 CONVERSION TIME (ms) 40 VCC = 5.5V, 4.1V, 2.7V 38 36 34 32 30 -45 -25 CONVERSION TIME (ms) 22 21 20
Conversion Period vs Temperature 60Hz Mode
VCC = 5.5V, 4.1V, 2.7V 19 18 17 16 15 -45 -25
35 15 55 -5 TEMPERATURE (C)
75
95
2451 G15
35 15 55 -5 TEMPERATURE (C)
75
95
2451 G16
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LTC2451 PIN FUNCTIONS
GND (Pin 1, 5): Ground. Connect to a ground plane through a low impedance connection. REF- (Pin 2), REF+ (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, remains more positive than the negative reference input, REF-, by at least 2.5V. The differential reference voltage (VREF = REF+ to REF-) sets the full-scale range. VCC (Pin 4): Positive Supply Voltage. Bypass to GND (Pin 1) with a 10F capacitor in parallel with a low series inductance 0.1F capacitor located as close to the part as possible. IN (Pin 6): Analog Input. IN's single-ended input range is VREF- to VREF+. SCL (Pin 7): Serial Clock Input of the I2C Interface. The LTC2451 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of SCL and output through the SDA pin on the falling edges of SCL. SDA (Pin 8): Bidirectional Serial Data Line of the I2C Interface. The conversion result is output through the SDA pin. The pin is high impedance unless the LTC2451 is in the data output mode. While the LTC2451 is in the data output mode, SDA is an open-drain pull-down (which requires an external 1.7k pull-up resistor to VCC). Exposed Pad (Pin 9): Ground. Must be soldered to PCB ground.
BLOCK DIAGRAM
3 REF + 4 VCC
I2C INTERFACE 6 IN 16-BIT A/D CONVERTER INTERNAL OSCILLATOR
SCL SDA
7 8
2
REF -
1
GND 1, 5, 9
2451 BD
APPLICATIONS INFORMATION
CONVERTER OPERATION Converter Operation Cycle The LTC2451 is a low power, delta-sigma analog-todigital converter with an I2C interface. Its operation, as shown in Figure 1, is composed of three successive states: conversion, sleep, and data input/output. Initially, at power-up, the LTC2451 is set to its default 60Hz mode and performs a conversion. Once the conversion is complete, the device enters the sleep state. While in the sleep state, power consumption is reduced by several orders of magnitude. The part remains in the sleep state as long it is not addressed for a Read or Write operation. The conversion result is held indefinitely in a static shift register while the part is in the sleep state. The device will not acknowledge an external request during the conversion state. After a conversion is finished, the device is ready to accept a Read/Write request. The LTC2451's address is hardwired at 0010100. Once the LTC2451 is addressed for a Read operation, the device
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LTC2451 APPLICATIONS INFORMATION
POWER-ON RESET CONVERSION
if the power supply voltage, VCC, is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Ease of Use The LTC2451 data output has no latency, filter settling delay, or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. In the 30Hz mode, the LTC2451 performs offset calibrations during every conversion. This calibration is transparent to the user and has no effect upon the cyclic operation previously described. The advantage of continuous calibration is stability of the ADC performance with respect to time and temperature. The LTC2451 includes a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta-sigma architectures. This allows external filter networks to interface directly to the LTC2451. Since the average input sampling current is 50nA, an external RC lowpass filter using a 1k and 0.1F results in less than 1LSB additional error. Reference Voltage Range This converter accepts a truly differential external reference voltage. The voltage range for the REF+ and REF- pins covers the entire operating range of the device (GND to VCC). For correct converter operation, VREF+ - VREF- 2.5V. The LTC2451 differential reference input range is 2.5V to VCC. For the simplest operation, REF+ can be shorted to VCC and REF- can be shorted to GND. Input Voltage Range Ignoring offset and full-scale errors, the converter will theoretically output an "all zero" digital result when the input is at VREF- (a zero scale input) and an "all one" digital result when the input is at VREF+ (a full-scale input). In an underrange condition, for all input voltages less than the voltage corresponding to output code 0, the converter will
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SLEEP
NO
READ/WRITE
ACKNOWLEDGE
YES DATA INPUT/OUTPUT
NO
STOP OR READ 16 BITS YES
2451 F01
Figure 1. State Diagram
begins outputting the conversion result under the control of the serial clock (SCL). There is no latency in the conversion result. The data output is 16 bits long and outputs from MSB to LSB. Data is updated on the falling edges of SCL, allowing the user to reliably latch data on the rising edge of SCL. In Write operation, the device accepts one configuration byte and the data is shifted in on the rising edges of SCL. A new conversion is initiated by a Stop condition following a valid Read or Write operation, or by the conclusion of a complete Read cycle (all 16 bits read out of the device). Power-Up Sequence When the power supply voltage, VCC, applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2451 starts a conversion cycle and follows the succession of states described in Figure 1. The first conversion result following POR is accurate within the specifications of the device
8
LTC2451 APPLICATIONS INFORMATION
generate the output code 0. In an overrange condition, for all input voltages greater than the voltage corresponding to output code 65535, the converter will generate the output code 65535. I2C INTERFACE The LTC2451 communicates through an I2C interface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. The connected devices can only pull the data line (SDA) low and never drive it high. SDA is externally connected to the supply through a pull-up resistor. When the data line is free, it is pulled high through this resistor. Data on the I2C bus can be transferred at rates up to 100k/s in the standard mode and up to 400k/s in the fast mode. The VCC power should not be removed from the device when the I2C bus is active to avoid loading the I2C bus lines through the internal ESD protection diodes. Each device on the I2C bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Devices addressed by the master are considered a slave. The address of the LTC2451 is 0010100. The LTC2451 can only be addressed as a slave. It can only transmit the last conversion result. The serial clock line, SCL, is always an input to the LTC2451 and the serial data line, SDA, is bidirectional. Figure 2 shows the definition of the I2C timing. The Start and Stop Conditions A Start (S) condition is generated by transitioning SDA from high to low while SCL is high. The bus is considered to be busy after the Start condition. When the data transfer is finished, a Stop (P) condition is generated by transitioning SDA from low to high while SCL is pulled high. The bus is free after a Stop is generated. Start and Stop conditions are always generated by the master. When the bus is in use, it stays busy if a Repeated Start (Sr) is generated instead of a Stop condition. The Repeated Start (Sr) conditions are functionally identical to the Start (S). Data Transferring After the Start condition, the I2C bus is busy and data transfer can begin between the master and the addressed slave. Data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ACK) bit. The master releases the SDA line during the ninth SCL clock cycle. The slave device can issue an ACK by pulling SDA low or issue a Not Acknowledge (NAK) by leaving the SDA line high impedance (the external pull-up resistor will hold the line high). Change of data only occurs while the clock line (SCL) is low. Data Format After a Start condition, the master sends a 7-bit address (factory set at 0010100), followed by a Read request (R) or Write request (W) bit. The bit R is 1 for a Read request and 0 for a Write request. If the 7-bit address agrees with the LTC2451's address, the device is selected. When the device is addressed during the conversion state, it does not accept the request and issues a NAK by leaving the SDA line high. If the conversion is complete, the LTC2451 issues an ACK by pulling the SDA line low.
SDA tf tLOW tr tSU(DAT) tf tHD(SDA) tSP tr tBUF
SCL tHD(STA) S tHD(DAT) tHIGH tSU(STA) Sr tSU(STO) P S
2451 F02
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
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LTC2451 APPLICATIONS INFORMATION
The user can send one byte of data into the LTC2451 following a Write request and an ACK. The sequence is shown in Figure 3. The Write sequence is used solely to set the conversion speed. The default conversion speed is 60Hz. The user can specify a 30Hz conversion speed by setting the eighth bit (S30) = 1, or specify a 60Hz conversion speed by setting the eighth bit (S30) = 0. After a Read request and an ACK, the LTC2451 can output data, as shown in Figure 4. The data output stream is 16 bits long and is shifted out on the falling edges of SCL. The first bit is the MSB (D15) and is followed by successively less significant bits (D14, D13 ...) until the LSB (D0) is output by the LTC2451. This sequence is summarized in Figure 5.
1 SCL 7 8 9 1 2 3
OPERATION SEQUENCE Continuous Read Conversions from the LTC2451 can be continuously read (see Figure 7). At the end of a Read operation, a new conversion automatically begins. At the conclusion of the conversion cycle, the next result may be read using the method described above. If the conversion cycle is not concluded and a valid address selects the device, the LTC2451 generates a NAK signal indicating the conversion cycle is in progress.
4
5
6
7
8
9
SDA
7-BIT ADDRESS
W
S30
S30 = 1: 30Hz MODE S30 = 0: 60Hz MODE
START BY MASTER SLEEP
ACK BY LTC2451 DATA INPUT
ACK BY MASTER
2451 F03
Figure 3. Timing Diagram for Write Sequence
1 SCL 7 8 9 1 2 3 8 9 1 2 3 8 9
SDA
7-BIT ADDRESS
R
D15 MSB
D14
D13
D8
D7
D6
D5
D0 LSB
START BY MASTER SLEEP
ACK BY LTC2451
ACK BY MASTER DATA OUTPUT
NACK BY MASTER CONVERT
2451 F04
Figure 4. Timing Diagram for Read Sequence
S CONVERSION
7-BIT ADDRESS (0010100) SLEEP
R
ACK
READ DATA OUTPUT
P CONVERSION
2451 F05
Figure 5. Conversion Sequence
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LTC2451 APPLICATIONS INFORMATION
Continuous Read/Write Once the conversion cycle is concluded, the LTC2451 can be written to, and then read from, using the Repeated Start (Sr) command. Figure 7 shows a cycle which begins with a data Write, a Repeated Start, followed by a Read, and concluded with a Stop command. The following conversion begins after all 16 bits are read out of the device, or after the Stop command, and uses the newly programmed configuration. Discarding a Conversion Result and Initiating a New Conversion with Optional Configuration Updating At the conclusion of a conversion cycle, a Write cycle can be initiated. Once the Write cycle is acknowledged, a Stop (P) command initiates a new conversion. If a new configuration is required, this data can be written into the device and a Stop command initiates a new conversion (see Figure 8). Synchronizing the LTC2451 with the Global Address Call The LTC2451 can also be synchronized with the global address call (see Figure 9). To achieve this, the LTC2451 must first have completed the conversion cycle. The
S CONVERSION 7-BIT ADDRESS (0010100) SLEEP R ACK READ DATA OUTPUT P CONVERSION
master issues a Start, followed by the LTC2451 global address 1110111, and a Write request. The LTC2451 will be selected and acknowledge the request. If desired, the master then sends the Write byte to program the 30Hz or 60Hz mode. After the optional Write byte, the master ends the Write operation with a Stop. This will update the configuration registers (if a Write byte was sent) and initiate a new conversion on the LTC2451, as shown in Figure 9. In order to synchronize the start of the conversion without affecting the configuration registers, the Write operation can be aborted with a Stop. This initiates a new conversion on the LTC2451 without changing the configuration registers. PRESERVING THE CONVERTER ACCURACY The LTC2451 is designed to dramatically reduce the conversion result's sensitivity to device decoupling, PCB layout, antialiasing circuits, line and frequency perturbations. Nevertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels Due to the nature of CMOS logic, it is advisable to keep input digital signals near GND or VCC. Voltages in the
S 7-BIT ADDRESS (0010100) SLEEP R ACK READ DATAOUTPUT P CONVERSION
2451 F06
Figure 6. Consecutive Reading at the Same Configuration
S CONVERSION
7-BIT ADDRESS (0010100) SLEEP
W ACK
WRITE DATA INPUT
Sr
7-BIT ADDRESS (0010100) ADDRESS
R
ACK
READ
P CONVERSION
2451 F05
DATA OUTPUT
Figure 7. Write, Read, Start Conversion
S CONVERSION
7-BIT ADDRESS (0010100) SLEEP
W ACK
WRITE (OPTIONAL) DATA INPUT
P CONVERSION
2451 F08
Figure 8. Start a New Conversion without Reading Old Conversion Result
S
GLOBAL ADDRESS (1110111) SLEEP
W
ACK
WRITE (OPTIONAL) DATA INPUT
P CONVERSION
2451 F09
Figure 9. Synchronize the LTC2451 with the Global Address Call
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LTC2451 APPLICATIONS INFORMATION
range of 0.5V to VCC - 0.5V may result in additional current leakage from the part. Driving VCC and GND In relation to the VCC and GND pins, the LTC2451 combines internal high frequency decoupling with damping elements, which reduce the ADC performance sensitivity to PCB layout and external components. Nevertheless, the very high accuracy of this converter is best preserved by careful low and high frequency power supply decoupling. A 0.1F, high quality, ceramic capacitor in parallel with a 10F ceramic capacitor should be connected between the VCC and GND pins, as close as possible to the package. The 0.1F capacitor should be placed closest to the ADC. It is also desirable to avoid any via in the circuit path, starting from the converter VCC pin, passing through these two decoupling capacitors, and returning to the converter GND pin. The area encompassed by this circuit path, as well as the path length, should be minimized. Very low impedance ground and power planes, and star connections at both VCC and GND pins, are preferable. The VCC pin should have three distinct connections: the first to the decoupling capacitors described above, the second to the ground return for the input signal source, and the third to the ground return for the power supply voltage source. Driving REF+ and REF - A simplified equivalent circuit for REF+ and REF - is shown in Figure 10. Like all other A/D converters, the LTC2451 is only as accurate as the reference it is using. Therefore, it is important to keep the reference line quiet by careful low and high frequency power supply decoupling. The LT6660 reference is an ideal match for driving the LTC2451's REF+ pin. The LTC6660 is available in a 2mm x 2mm DFN package with 2.5V, 3V, 3.3V and 5V options. A 0.1F, high quality, ceramic capacitor in parallel with a 10F ceramic capacitor should be connected between the REF +/REF - and GND pins, as close as possible to the package. The 0.1F capacitor should be placed closest to the ADC.
REF + ILEAK CEQ 0.35pF (TYP) VCC ILEAK RSW 15k (TYP)
VCC ILEAK IN ILEAK
RSW 15k (TYP)
VCC ILEAK REF - ILEAK
RSW 15k (TYP)
2451 F10
Figure 10. LTC2451 Analog Input and Reference Pins Equivalent Circuit
Driving IN The input drive requirements can best be analyzed using the equivalent circuit of Figure 11. The input signal, VSIG, is connected to the ADC input pin (IN) through an equivalent source resistance RS . This resistor includes both the actual generator source resistance and any additional optional resistors connected to the input pin. An optional input capacitor, CIN, is also connected between the ADC input pin and GND. This capacitor is placed in parallel with the ADC input parasitic capacitance, CPAR. Depending on the PCB layout, CPAR has typical values between 2pF and 15pF. In addition, the equivalent circuit of Figure 11 includes the converter equivalent internal resistor, RSW, and sampling capacitor, CEQ. There are some immediate trade-offs in RS and CIN without needing a full circuit analysis. Increasing RS and CIN can provide the following benefits: 1. Due to the LTC2451's input sampling algorithm, the input current drawn by the input pin (IN) over a conversion cycle is 50nA. A high RS * CIN attenuates the high frequency components of the input current, and RS values up to 1k result in <1LSB additional INL.
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12
LTC2451 APPLICATIONS INFORMATION
2. The bandwidth from VSIG is reduced at the input pin. This bandwidth reduction isolates the ADC from high frequency signals, and as such provides simple antialiasing and input noise reduction. 3. Switching transients generated by the ADC are attenuated before they go back to the signal source. 4. A large CIN gives a better AC ground at the input pin, helping reduce reflections back to the signal source. 5. Increasing RS protects the ADC by limiting the current during an outside-the-rails fault condition. There is a limit to how large RS * CIN should be for a given application. Increasing RS beyond a given point increases the voltage drop across RS due to the input current, to the point that significant measurement errors exist. Additionally, for some applications, increasing the RS * CIN product too much may unacceptably attenuate the signal at frequencies of interest. For most applications, it is desirable to implement CIN as a high quality 0.1F ceramic capacitor and RS 1k. This capacitor should be located as close as possible to the input pin. Furthermore, the area encompassed by this circuit path, as well as the path length, should be minimized.
RS IN
In the case of a 2-wire sensor that is not remotely grounded, it is desirable to split RS and place series resistors in the ADC input line and in the sensor ground return line, which should be tied to the ADC GND pin using a star connection topology. Figure 12 shows the measured LTC2451 INL versus the input voltage as a function of RS value with an input capacitor CIN = 0.1F. In some cases, RS can be increased above these guidelines. The input current is negligible when the ADC is either in sleep or I/O modes. Thus, if the time constant of the input RC circuit = RS * CIN , is of the same order of magnitude or longer than the time periods between actual conversions, then one can consider the input current to be reduced correspondingly. These considerations need to be balanced out by the input signal bandwidth. The 3dB bandwidth 1/(2RSCIN). Finally, if the recommended choice for CIN is unacceptable for the user's specific application, an alternate strategy is to eliminate CIN and minimize CPAR and RS. In practical terms, this configuration corresponds to a low impedance sensor directly connected to the ADC through minimum length
VCC ILEAK ILEAK RSW 15k (TYP) CEQ 0.35pF (TYP)
+ -
VSIG
CIN
CPAR
ICONV
2451 F11
Figure 11. LTC2451 Input Drive Equivalent Circuit
16 12 8 INL(LSB) RS = 1k RS = 0 RS = 10k -8 -12 -16 0 1 3 INPUT VOLTAGE (V) 2 4 5
2451 F12
8 6 4 INL (LSB) 2 0 -2 RS = 0 -4 -6 -8 0 0.5 1 1.5 2 2.5 3 3.5 INPUT VOLTAGE (V) 4 4.5 5
2451 F13
4 0 -4
RS = 1k
RS = 10k
Figure 12. Measured INL vs Input Voltage, CIN = 0.1F VCC = 5V, TA = 25C ,
Figure 13. Measured INL vs Input Voltage, CIN = 0, VCC = 5V, TA = 25C
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13
LTC2451 APPLICATIONS INFORMATION
traces. Actual applications include current measurements through low value sense resistors, temperature measurements, low impedance voltage source monitoring, and so on. The resultant INL versus VIN is shown in Figure 13. The measurements of Figure 13 include a capacitor CPAR corresponding to a minimum sized layout pad and a minimum width input trace of about 1" length. Signal Bandwidth and Noise Equivalent Input Bandwidth The LTC2451 includes a sinc1 type digital filter with the first notch located at f0 = 60Hz. As such, the 3dB input signal bandwidth is 26.54Hz. The calculated LTC2451 input signal attenuation versus frequency over a wide frequency range is shown in Figure 14. The calculated LTC2451 input signal attenuation with low frequencies is shown in Figure 15.
0 INPUT SIGNAL ATTENUATIOIN (dB) INPUT SIGNAL ATTENUATION (dB)
The converter noise level is about 1.4VRMS , and can be modeled by a white noise source connected at the input of a noise-free converter. For a simple system noise analysis, the input drive circuit can be modeled as a single-pole equivalent circuit characterized by a pole location, fi , and a noise spectral density, ni . If the converter has an unlimited bandwidth, or at least a bandwidth substantially larger than fi , then the total noise contribution of the external drive circuit would be: Vn = ni / 2 * fi The total system noise level can then be estimated as the square root of the sum of (Vn2) and the square of the LTC2451 noise floor (~2V2).
0 -5 -10 -15 -20 -25 -30 -35 -40 -45
-20
-40
-60
-80
-100 0 2.5 5.0 7.5 1.00 1.25 1.50
2451 F14
-50 INPUT SIGNAL FREQUENCY (MHz)
0
60 120 180 240 300 360 420 480 540 600 INPUT SIGNAL FREQUENCY (Hz)
2451 F15
Figure 14. LTC2451 Input Signal Attentuation vs Frequency
Figure 15. LTC2451 Input Signal Attenuation vs Frequency (Low Frequencies)
TYPICAL APPLICATIONS
Easy Active Input
PRECONDITIONED SENSOR WITH VOLTAGE OUTPUT
Easy Passive Input
V+ VOUT GND
1k LTC2451 100nF
2451 TA02
RS < 1k LTC2451 100nF
2451 TA03
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14
LTC2451 PACKAGE DESCRIPTION
DDB Package 8-Lead Plastic DFN (3mm x 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
0.61 0.05 (2 SIDES) 0.70 0.05 2.55 0.05 1.15 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.20 0.05 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 2.00 0.10 (2 SIDES) 0.56 0.05 (2 SIDES) 0.75 0.05 0.25 PIN 1 R = 0.20 OR 0.25 45 CHAMFER
(DDB8) DFN 0905 REV B
3.00 0.10 (2 SIDES)
R = 0.05 TYP
R = 0.115 TYP 5
0.40 8
0.10
0.200 REF
4 0.05 2.15 0.05 (2 SIDES)
1 0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0 - 0.05
BOTTOM VIEW--EXPOSED PAD
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15
LTC2451 PACKAGE DESCRIPTION
TS8 Package 8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
0.52 MAX 0.65 REF 2.90 BSC (NOTE 4)
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 - 1.75 (NOTE 4) PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.65 BSC
0.22 - 0.36 8 PLCS (NOTE 3)
0.80 - 0.90 0.20 BSC 1.00 MAX DATUM `A' 0.01 - 0.10
0.30 - 0.50 REF
NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
0.09 - 0.20 (NOTE 3)
1.95 BSC
TS8 TSOT-23 0802
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16
LTC2451 REVISION HISTORY
REV F DATE 6/10 DESCRIPTION Added text to I2C Interface section
(Revision history begins at Rev F)
PAGE NUMBER 9
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC2451 TYPICAL APPLICATION
Thermistor Measurement
5k
10k IN THERMISTOR 1k TO 10k 100nF
REF + LTC2451 REF -
VCC
SCL SDA
GND
2451 TA04
RELATED PARTS
PART NUMBER LT1236A-5 LT1461 LT1790 LTC1860/LTC1861 LTC1860L/LTC1861L LTC1864/LTC1865 LTC1864L/LTC1865L LTC2440 LTC2480 LTC2481 LTC2482 LTC2483 LTC2484 LTC2485 LTC6241 LT6660 LTC2450 LTC2450-1 LTC2453 DESCRIPTION Precision Bandgap Reference, 5V Micropower Series Reference, 2.5V Micropower Precision Reference in TSOT-23-6 Package 12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC 16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 16-Bit, 3V, 1-/2-Channel 150ksps SAR ADC 24-Bit No Latency TMADC 16-Bit, Differential Input, No Latency ADC, with PGA, Temperature Sensor, SPI 16-Bit, Differential Input, No Latency ADC, with PGA, Temperature Sensor, I2C 16-Bit, Differential Input, No Latency ADC, SPI 16-Bit, Differential Input, No Latency ADC, I2C 24-Bit, Differential Input, No Latency ADC, SPI 24-Bit, Differential Input, No Latency ADC, I2C Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp Micropower References in 2mm x 2mm DFN Package, 2.5V, 3V, 3.3V, 5V Easy-to-Use, Ultra-Tiny 16-Bit ADC Easy-to-Use, Ultra-Tiny 16-Bit ADC I2C, Differential, Ultra-Tiny 16-Bit ADC COMMENTS 0.05% Max, 5ppm/C Drift 0.04% Max, 3ppm/C Drift 60A Max Supply Current, 10ppm/C Max Drift, 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V and 5V Options 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages 200nVRMS Noise, 8kHz Output Rate, 15ppm INL Easy DriveTM Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package Easy Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package 550nVP-P Noise, 125V Offset Max 20ppm/C Maximum Drift, 0.2% Max 2 LSB INL, 50nA Sleep Current, Tiny 2mm x 2mm DFN-6 Package, 30Hz Output Rate 2 LSB INL, 50nA Sleep Current, Tiny 2mm x 2mm DFN-6 Package, 60Hz Output Rate 2 LSB INL, 50nA Sleep Current, 3mm x 2mm DFN-8 and TSOT-8 Packages, 60Hz Output Rate
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18 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0610 REV F * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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